1. Field of the Invention
The present invention relates to a method of synchronizing dual clock frequencies and, more particularly, to a method of synchronizing a relatively high frequency clock and a relatively low frequency clock applied to various components of a computer system through generating a synchronization signal.
2. Description of the Related Art
In today's computer system, for exhibiting a better performance, a microprocessor of the computer system is operated at the highest possible frequency while other components of the computer system are operated at a lower frequency limited by the system board technology. More specifically, as shown in FIG. 1(a), a general computer system 10 mainly includes a microprocessor 11, an input/output (I/O) device 12 for allowing a computer user to communicate information and commands to the microprocessor 11, a display device 13 for displaying information to the computer user, a data storage device 14 for storing information, and an external memory 15 for storing instructions and data used by the microprocessor 11.
The microprocessor 11 is operated in accordance with a core clock having a higher frequency, and is coupled to a system bus 16. The system bus 16 includes the address, data, and control lines necessary for transferring data between various constituting blocks of the computer system 10. All of the I/O device 12, the display device 13, the data storage device 14, and the external memory 15 are also coupled to the system bus 16. On the system bus 16, the information is transferred in accordance with a bus clock having a lower frequency than that of the core clock. Furthermore, all of the I/O device 12, the display device 13, the data storage device 14, and the external memory 15 coupled to the system bus 16 are operated in accordance with the bus clock having the lower frequency.
Therefore, it has become a very important subject in the field of digital signal processing technology: how to synchronize the data transfer between the microprocessor operated in accordance with the higher frequency core clock and the other components operated in accordance with the lower frequency bus clock.
FIG. 1(b) shows an example of a conventional method of synchronizing dual clock frequencies. Referring to FIG. 1(b), the bus clock BUS_CK is supplied to a bus device 20 as a clock frequency used therein, and is input to a phase-locked loop 21 of the microprocessor 11 for generating the core clock CORE_CK. The core clock CORE_CK is used as a clock frequency inside the microprocessor 11. A core 22 of the microprocessor 11 is provided with two clock trees 23 and 24, to which the core clock CORE_CK and the bus clock BUS_CK are applied, respectively. A synchronization circuit 25 makes the core clock CORE_CK and the bus clock BUS_CK synchronized. This conventional method has a drawback regarding with the necessary use of two clock trees 23 and 24.
FIG. 1(c) shows another example of a conventional method of synchronizing dual clock frequencies. Referring to FIG. 1(c), a frequency divider 26 makes the core clock CORE_CK divided by N to thereby generate the bus clock BUS_CK for the bus device 20. In addition, the frequency divider 26 outputs a bus clock enable signal BUSCK_EN to the microprocessor 11. However, in normal application of the phase-locked loop instead of the frequency divider 26, there is no way to generate the bus clock enable signal BUSCK_EN by employing this conventional method.